AI inference performance.
I’m an electronic engineer from Dublin with a background in digital hardware, embedded software, and electronics. I’m also a classical flautist and pianist, and a former principal player with the National Youth Orchestra of Ireland.
I’m currently working on performance engineering for real-time AI inference, with a particular interest in physical-AI workloads such as VLAs and world models. I’m interested in how modern inference workloads execute on GPUs, where their latency and memory bottlenecks come from, and how those characteristics can be used to evaluate and shape future accelerator architectures.
At ASML, I built an FPGA–Linux diagnostic and calibration platform for precision-motion hardware. The FPGA handled real-time data acquisition and deterministic processing, while Linux handled configuration, diagnostics, and live visualisation.
In Formula Student, I owned the electrical architecture of a 300 V electric race car from scratch, designed and brought up more than ten custom PCBs, and built and validated its 75-cell battery-management system.
Owned the car’s rule-critical electrical architecture, designed and brought up more than ten custom PCBs, and built the validated 75-cell BMS across hardware, embedded firmware, diagnostics, and desktop tooling.
Implemented and placed-and-routed three MAC-array architectures to measure when compute sharing is worth its fixed twofold latency cost—and when it only saves resources the design does not need.
Implemented a fixed-function MNIST inference pipeline with signed fixed-point arithmetic, reaching 4.7 ms compute latency at 100 MHz and 92.2% accuracy.
Implemented a cycle-accurate NASDAQ ITCH ingestion pipeline with Ethernet framing, CRC verification, and backpressure-safe parsing in 38 cycles.