Electronic Engineering · FPGA · Embedded Systems · PCB Design

Keelan Reilly

Building hardware systems from RTL accelerators to embedded firmware and custom PCBs. Work spans FPGA implementation, mixed-signal board design, embedded C on STM32, and the verification and tooling that connects them.

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Work

Formula Student BMS — 75-Cell Hardware and Firmware Stack

2026

A hardware-led Formula Student BMS project covering STM32 master-board design, LTC6812 cell-monitoring hardware, dual isoSPI chains, pack measurement, safety permission logic, embedded firmware, desktop tooling, and pre-hardware validation.

75 cells LTC6812 cell-monitoring ICs Dual Cell + temperature, separate chip selects Simulator target Full protocol + UI exercised before first power-on

Compute Sharing in FPGA MAC Arrays Isn't a Smooth Tradeoff

2026

A measured comparison of FPGA MAC array variants showing that compute sharing is only worth its fixed cost under genuine resource pressure.

33 cycles Dedicated MAC array 65 cycles Fixed ~2× penalty for both shared designs 100% DSP-eliminating variant, no change to scheduling

Quantised CNN Inference Accelerator

2025

A fixed-function FPGA CNN inference accelerator implemented in SystemVerilog. The project explores how architectural decisions around data layout, precision, and scheduling affect performance and flexibility.

~466k cycles ≈ 4.7 ms @ 100 MHz ~7.28M cycles ≈ 73 ms @ 115,200 baud ~92.2% Float baseline: ~94.3% (1 epoch)

FPGA Market Data Parser (Low-Latency Pipeline)

2025

This project implements a low-latency market data ingestion pipeline in SystemVerilog. I built it to understand how protocol handling, backpressure, and control timing shape end-to-end latency in real hardware pipelines.

~38 cycles ≈ 152 ns @ 250 MHz (simulation) 250 MHz Closed with positive slack in Vivado Cycle-accurate Verilator + Python reference models